Bipolar transistors are important for high-frequency applications, such as optical data communication, and for RF power applications, such as power amplifier modules in wireless handset applications. Generally, it is important in RF power applications to have a bipolar transistor with both a good high-frequency performance and a high base-collector junction breakdown voltage (BVCB0) to meet ruggedness demands, especially during load mismatch conditions. This speed-breakdown trade-off is, amongst others, influenced by the drift region in the collector region of the bipolar transistor. A higher doping concentration of the collector drift region increases the speed of the bipolar transistor, but reduces the breakdown voltage between the collector region and any other adjacent region, such as the base region.
One way of improving the speed-breakdown trade-off is by applying the reduced surface field (Resurf) effect. In “A new Sub-Micron 24V SiGe:C Resurf HBT”, by J. Melai et al, ISPSD, 2004, it is disclosed that the Resurf effect comprises the reshaping of the electric field distribution in the collector drift region for a reverse bias situation such that a more uniform electric field distribution with a reduced maximum electric field is formed. The BVCB0 of the bipolar transistor is thereby increased or, alternatively, for the same BVCB0 the doping concentration of the collector region can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. A method to implement the Resurf effect in a bipolar transistor is the addition of a field plate, which is electrically isolated from the collector drift region by a dielectric layer. By applying a suitable voltage on the field plate, the electric field of the collector drift region is reshaped into the more uniform electric field distribution. The method of manufacturing a bipolar transistor with a field plate, which is disclosed in “A new Sub-Micron 24V SiGe:C Resurf HBT”, by J. Melai et al, ISPSD, 2004, starts with the formation of a sub-collector region in a semiconductor substrate followed by the epitaxial growth of a collector drift region on the sub-collector region. Then standard shallow trench isolation (STI) regions are formed and a base layer is epitaxially grown on the collector drift region. On the base layer a hard mask layer is deposited and patterned using photolithography, thereby defining and masking the area where the bipolar transistor will be formed and forming extrinsic base windows in the hard mask that expose a part of the base layer, which adjoins the area where the bipolar transistor will be formed and which extends over a part of the collector drift region and a part of the STI regions. Then trenches are formed by removing the exposed base layer and etching the then exposed part of the collector drift region until the sub-collector region is exposed at the bottom of the trenches. A first sidewall of the trenches adjoins the collector drift region of the bipolar transistor and a second sidewall of the trenches adjoins the STI region. Then a TEOS (Tetraethyl Orthosilicate) layer is formed on the first and second sidewall of the trench by deposition and etch-back of TEOS. Subsequently the trenches are filled with undoped polysilicon up to the level of the base by deposition, CMP and dry etching techniques. Then an extrinsic base contact is made by deposition, planarization and etch-back of p-type polysilicon, partly filling the extinsic base windows and electrically contacting the undoped polysilicon in the trench and the base layer. After removal of the hard mask, an emitter region is formed on a part of the base layer that extends over the collector drift region using, amongst others, deposition and photolithography process steps.